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TS4972
1.2W AUDIO POWER AMPLIFIER WITH STANDBY MODE ACTIVE HIGH
s OPERATING FROM VCC = 2.5V to 5.5V s RAIL TO RAIL OUTPUT s 1.2W OUTPUT POWER @ Vcc=5V, THD=1%,
F=1kHz, with 8 Load PIN CONNECTIONS (Top View)
TS4972JT - FLIP CHIP
s ULTRA LOW CONSUMPTION IN STANDBY
MODE (10nA)
s 75dB PSRR @ 217Hz from 2.5 to 5V s LOW POP & CLICK s ULTRA LOW DISTORTION (0.05%) s UNITY GAIN STABLE s FLIP CHIP PACKAGE 8 x 300m bumps
DESCRIPTION The TS4972 is an Audio Power Amplifier capable of delivering 1.6W of continuous RMS ouput power into a 4 load @ 5V. This Audio Amplifier is exhibiting 0.1% distortion level (THD) from a 5V supply for a Pout = 250mW RMS. An external standby mode control reduces the supply current to less than 10nA. An internal shutdown protection is provided. The TS4972 has been designed for high quality audio applications such as mobile phones and to minimize the number of external components. The unity-gain stable amplifier can be configured by external gain setting resistors.
7
Vin
+
6
Vcc
5
Stdby
8
Vout1
Vout2
4
Vin
Gnd
Bypass
1
2
3
APPLICATIONS
TYPICAL APPLICATION SCHEMATIC
Cfeed Rfeed VCC 6 Audio Input Cin 7 Vin+ + RL 8 Ohms VCC Rin 1 VinVout 1 8 Cs
s Mobile Phones (Cellular / Cordless) s PDAs s Laptop/Notebook computers s Portable Audio Devices
ORDER CODE
Part Number TS4972IJT Temperature Range -40, +85C Package Marking J * 4972
VCC Rstb
AV = -1 3 5 Bypass Standby + Bias GND Cb 2
Vout 2
4
TS4972
J = Flip Chip Package - only available in Tape & Reel (JT))
January 2003
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TS4972
ABSOLUTE MAXIMUM RATINGS
Symbol VCC Vi Toper Tstg Tj Rthja Pd Supply voltage Input Voltage
2) 1)
Parameter
Value 6 GND to VCC -40 to + 85 -65 to +150 150 200 Internally Limited 2 200 Class A 250
4)
Unit V V C C C C/W kV V C
Operating Free Air Temperature Range Storage Temperature Maximum Junction Temperature Thermal Resistance Junction to Ambient 3) Power Dissipation
ESD Human Body Model ESD Machine Model Latch-up Latch-up Immunity Lead Temperature (soldering, 10sec)
1. 2. 3. 4. All voltages values are measured with respect to the ground pin. The magnitude of input signal must never exceed VCC + 0.3V / G ND - 0.3V Device is protected in case of over temperature by a thermal shutdown active @ 150C. Exceeding the power derating curves during a long period, involves abnormal operating condition.
OPERATING CONDITIONS
Symbol VCC VICM VSTB RL Rthja Supply Voltage Common Mode Input Voltage Range Standby Voltage Input : Device ON Device OFF Load Resistor Thermal Resistance Junction to Ambient
1)
Parameter
Value 2.5 to 5.5 GND to VCC - 1.2V GND VSTB 0.5V VCC - 0.5V VSTB VCC 4 - 32 90
Unit V V V C/W
1. With Heat Sink Surface = 125mm 2
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TS4972
ELECTRICAL CHARACTERISTICS VCC = +5V, GND = 0V, Tamb = 25C (unless otherwise specified)
Symbol ICC ISTANDBY Voo Po THD + N PSRR M GM GBP Parameter Supply Current No input signal, no load Standby Current 1) No input signal, Vstdby = Vcc, RL = 8 Output Offset Voltage No input signal, RL = 8 Output Power THD = 1% Max, f = 1kHz, RL = 8 Total Harmonic Distortion + Noise Po = 250mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8 Power Supply Rejection Ratio2) f = 217Hz, RL = 8, RFeed = 22K, Vripple = 200mV rms Phase Margin at Unity Gain RL = 8, CL = 500pF Gain Margin RL = 8, CL = 500pF Gain Bandwidth Product RL = 8 Min. Typ. 6 10 5 1.2 0.1 75 70 20 2 Max. 8 1000 20 Unit mA nA mV W % dB Degrees dB MHz
1. Standby mode is actived when Vstdby is tied to Vcc 2. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to Vcc @ f = 217Hz
VCC = +3.3V, GND = 0V, Tamb = 25C (unless otherwise specified)3)
Symbol ICC ISTANDBY Voo Po THD + N PSRR M GM GBP Parameter Supply Current No input signal, no load Standby Current 1) No input signal, Vstdby = Vcc, RL = 8 Output Offset Voltage No input signal, RL = 8 Output Power THD = 1% Max, f = 1kHz, RL = 8 Total Harmonic Distortion + Noise Po = 250mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8 Power Supply Rejection Ratio2) f = 217Hz, RL = 8, RFeed = 22K, Vripple = 200mV rms Phase Margin at Unity Gain RL = 8, CL = 500pF Gain Margin RL = 8, CL = 500pF Gain Bandwidth Product RL = 8 Min. Typ. 5.5 10 5 500 0.1 75 70 20 2 Max. 8 1000 20 Unit mA nA mV mW % dB Degrees dB MHz
1. Standby mode is actived when Vstdby is tied to Vcc 2. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to Vcc @ f = 217Hz 3. All electrical values are made by correlation between 2.6V and 5V measurements
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TS4972
ELECTRICAL CHARACTERISTICS VCC = 2.6V, GND = 0V, Tamb = 25C (unless otherwise specified)
Symbol ICC ISTANDBY Voo Po THD + N PSRR M GM GBP Parameter Supply Current No input signal, no load Standby Current 1) No input signal, Vstdby = Vcc, RL = 8 Output Offset Voltage No input signal, RL = 8 Output Power THD = 1% Max, f = 1kHz, RL = 8 Total Harmonic Distortion + Noise Po = 200mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8 Power Supply Rejection Ratio2) f = 217Hz, RL = 8, RFeed = 22K, Vripple = 200mV rms Phase Margin at Unity Gain RL = 8, CL = 500pF Gain Margin RL = 8, CL = 500pF Gain Bandwidth Product RL = 8 Min. Typ. 5.5 10 5 300 0.1 75 70 20 2 Max. 8 1000 20 Unit mA nA mV mW % dB Degrees dB MHz
1. Standby mode is actived when Vstdby is tied to Vcc 2. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to Vcc @ f = 217Hz
Components Rin Cin Rfeed Cs Cb Cfeed Rstb Gv
Functional Description Inverting input resistor which sets the closed loop gain in conjunction with Rfeed. This resistor also forms a high pass filter with Cin (fc = 1 / (2 x Pi x Rin x Cin)) Input coupling capacitor which blocks the DC voltage at the amplifier input terminal Feed back resistor which sets the closed loop gain in conjunction with Rin Supply Bypass capacitor which provides power supply filtering Bypass pin capacitor which provides half supply filtering Low pass filter capacitor allowing to cut the high frequency (low pass filter cut-off frequency 1 / (2 x Pi x Rfeed x Cfeed)) Pull-up resistor which fixes the right supply level on the standby pin Closed loop gain in BTL configuration = 2 x (Rfeed / Rin)
REMARKS 1. All measurements, except PSRR measurements, are made with a supply bypass capacitor Cs = 100F. 2. External resistors are not needed for having better stability when supply @ Vcc down to 3V. By the way, the quiescent current remains the same. 3. The standby response time is about 1s.
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TS4972
Fig. 1 : Open Loop Frequency Response
0 60 Gain Vcc = 5V RL = 8 Tamb = 25C -20 -40 -60
Phase (Deg)
40 Phase
Gain (dB)
Fig. 2 : Open Loop Frequency Response
0 60 Gain Vcc = 5V ZL = 8 + 560pF Tamb = 25C -20 -40 -60
Phase (Deg)
Phase (Deg)
40
Gain (dB)
Phase 20
-80 -100 -120
-80 -100 -120
20
0
-140 -160
0
-140 -160
-20
-180 -200
-20
-180 -200
-40 0.3
1
10
100
Frequency (kHz)
1000
10000
-220
-40 0.3
1
10
100 1000 Frequency (kHz)
10000
-220
Fig. 3 : Open Loop Frequency Response
80 60 40
Gain (dB)
Fig. 4 : Open Loop Frequency Response
80 60 40 Phase 20 0 -20 -40 0.3 Gain Vcc = 3.3V ZL = 8 + 560pF Tamb = 25C 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 -220 1 10 100 1000 Frequency (kHz) 10000 -240
Phase (Deg)
0 Gain Vcc = 33V RL = 8 Tamb = 25C -20 -40 -60 -100 -120 -140 -160 -180 -200 -220 -240
Phase (Deg) Gain (dB)
-80 Phase
20 0
-20 -40 0.3
1
10
100 1000 Frequency (kHz)
10000
Fig. 5 : Open Loop Frequency Response
Fig. 6 : Open Loop Frequency Response
80 Gain 60 40
Phase (Deg)
Gain (dB)
80 60 40
Gain (dB)
0 Gain Vcc = 2.6V RL = 8 Tamb = 25C -20 -40 -60 -80 Phase -100 -120 -140 -160 -180 -200 -220 -240
0 Vcc = 2.6V ZL = 8 + 560pF Tamb = 25C -20 -40 -60 -80 Phase -100 -120 -140 -160 -180 -200 -220 -240
20 0 -20 -40 0.3
20 0 -20 -40 0.3
1
10
100 1000 Frequency (kHz)
10000
1
10
100 1000 Frequency (kHz)
10000
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TS4972
Fig. 7 : Open Loop Frequency Response Fig. 8 : Open Loop Frequency Response
100 80 60 Gain
Gain (dB)
-80 Phase -100 -120
100 80 60
Phase (Deg)
-80 Phase -100 -120 -140 -160
Phase (Deg)
Gain
Gain (dB)
40 20 0 -20 -40 0.3
-140 -160 -180 Vcc = 5V CL = 560pF Tamb = 25C 1 10 100 1000 Frequency (kHz) 10000 -200
40 20 -180 0 -20 Vcc = 3.3V CL = 560pF Tamb = 25C 1 10 100 1000 Frequency (kHz) 10000 -200 -220 -240
-220
-40 0.3
Fig. 9 : Open Loop Frequency Response
100 80 60 Gain
Gain (dB)
-80 Phase -100 -120 -140 -160
Phase (Deg)
40 20 -180 0 -20 -40 0.3 Vcc = 2.6V CL = 560pF Tamb = 25C 1 10 100 1000 Frequency (kHz) 10000 -200 -220 -240
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TS4972
Fig. 10 : Power Supply Rejection Ratio (PSRR) vs Power supply Fig. 11 : Power Supply Rejection Ratio (PSRR) vs Feedback Capacitor
-30 Vripple = 200mVrms Rfeed = 22 Input = floating RL = 8 Tamb = 25C
-10 -20 -30
PSRR (dB)
-40
PSRR (dB)
-50
-40 -50 -60
Vcc = 5, 3.3 & 2.6V Cb = 1F & 0.1F Rfeed = 22k Vripple = 200mVrms Input = floating RL = 8 Tamb = 25C
Cfeed=0 Cfeed=150pF Cfeed=330pF
-60
Vcc = 5V, 3.3V & 2.6V Cb = 1F & 0.1F
-70 -70 -80 10 -80 10 Cfeed=680pF
100
1000 10000 Frequency (Hz)
100000
100
1000 10000 Frequency (Hz)
100000
Fig. 12 : Power Supply Rejection Ratio (PSRR) vs Bypass Capacitor
-10 Cb=1F -20 Cb=10F -30
PSRR (dB)
Fig. 13 : Power Supply Rejection Ratio (PSRR) vs Input Capacitor
-10 Cin=1F
-40 Cb=47F -50 -60
PSRR (dB)
Vcc = 5, 3.3 & 2.6V Rfeed = 22k Rin = 22k, Cin = 1F Rg = 100, RL = 8 Tamb = 25C
Cin=330nF -20 Cin=220nF
-30
Vcc = 5, 3.3 & 2.6V Rfeed = 22k, Rin = 22k Cb = 1F Rg = 100, RL = 8 Tamb = 25C
-40 Cin=100nF -50 Cin=22nF
-70 -80 10
Cb=100F 100 1000
Frequency (Hz)
10000
100000
-60 10
100
1000
Frequency (Hz)
10000
100000
Fig. 14 : Power Supply Rejection Ratio (PSRR) vs Feedback Resistor
-10 -20 -30
PSRR (dB)
-40 -50 -60
Vcc = 5, 3.3 & 2.6V Cb = 1F & 0.1F Vripple = 200mVrms Input = floating RL = 8 Tamb = 25C
Rfeed=110k Rfeed=47k
Rfeed=22k -70 Rfeed=10k -80 10 100 1000 10000 Frequency (Hz) 100000
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TS4972
Fig. 15 : Pout @ THD + N = 1% vs Supply Voltage vs RL Fig. 16 : Pout @ THD + N = 10% vs Supply Voltage vs RL
1.6
2.0
Output power @ 10% THD + N (W)
Gv = 2 & 10 Cb = 1F F = 1kHz BW < 125kHz Tamb = 25C 8 6 4
Output power @ 1% THD + N (W)
1.4 1.2 1.0 0.8 0.6 0.4 0.2
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2
Gv = 2 & 10 Cb = 1F F = 1kHz BW < 125kHz Tamb = 25C
8 4 6
16
16
32 3.0 3.5 4.0 Power Supply (V) 4.5 5.0
32 3.0 3.5 4.0 Power Supply (V) 4.5 5.0
0.0 2.5
0.0 2.5
Fig. 17 : Power Dissipation vs Pout
1.4 Vcc=5V 1.2 F=1kHz THD+N<1% 1.0 0.8 0.6 0.4 0.2 RL=16 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Output Power (W) 1.4 1.6 RL=8
Fig. 18 : Power Dissipation vs Pout
0.6 Vcc=3.3V F=1kHz 0.5 THD+N<1%
Power Dissipation (W)
Power Dissipation (W)
RL=4
RL=4
0.4 0.3 0.2 RL=8 0.1 RL=16 0.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Output Power (W)
Fig. 19 : Power Dissipation vs Pout
0.40 0.35 Vcc=2.6V F=1kHz THD+N<1% RL=4
Fig. 20 : Power Derating Curves
Flip-Chip Package Power Dissipation (W)
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 No Heat sink Heat sink surface = 125mm (See demoboard)
2
Power Dissipation (W)
0.30 0.25 0.20 0.15 RL=8 0.10 0.05 0.00 0.0 RL=16 0.1 0.2 Output Power (W) 0.3
0.4
0
25
50
75
100
125
150
Ambiant Temperature ( C)
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TS4972
Fig. 21 : THD + N vs Output Power
10 RL = 4 Vcc = 5V Gv = 2 Cb = Cin = 1F BW < 125kHz Tamb = 25C
Fig. 22 : THD + N vs Output Power
10 RL = 4, Vcc = 5V Gv = 10 Cb = Cin = 1F BW < 125kHz, Tamb = 25C
20kHz
20kHz
0.1 20Hz 0.01 1E-3 1kHz
THD + N (%)
THD + N (%)
1
1
0.1 20Hz 1kHz
0.01 0.1 Output Power (W)
1
0.01 1E-3
0.01 0.1 Output Power (W)
1
Fig. 23 : THD + N vs Output Power
10 RL = 4, Vcc = 3.3V Gv = 2 Cb = Cin = 1F BW < 125kHz Tamb = 25C 20kHz 0.1
Fig. 24 : THD + N vs Output Power
10 RL = 4, Vcc = 3.3V Gv = 10 Cb = Cin = 1F BW < 125kHz Tamb = 25C
THD + N (%)
1
THD + N (%)
1
20kHz
0.1
20Hz
20Hz 0.01 1E-3 0.01 0.1 Output Power (W)
1kHz 1 0.01 1E-3 0.01 0.1 Output Power (W)
1kHz 1
Fig. 25 : THD + N vs Output Power
10 RL = 4, Vcc = 2.6V Gv = 2 Cb = Cin = 1F BW < 125kHz Tamb = 25C
Fig. 26 : THD + N vs Output Power
10 RL = 4, Vcc = 2.6V Gv = 10 Cb = Cin = 1F BW < 125kHz Tamb = 25C
THD + N (%)
1
THD + N (%)
1
20Hz
20kHz 0.1
0.1
20kHz
20Hz 0.01 1E-3
1kHz 0.01 1E-3
1kHz 0.01 0.1 Output Power (W)
0.01 0.1 Output Power (W)
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TS4972
Fig. 27 : THD + N vs Output Power
10 RL = 8 Vcc = 5V Gv = 2 Cb = Cin = 1F 1 BW < 125kHz Tamb = 25C 20kHz 0.1
Fig. 28 : THD + N vs Output Power
10 RL = 8 Vcc = 5V Gv = 10 Cb = Cin = 1F 1 BW < 125kHz Tamb = 25C
THD + N (%)
THD + N (%)
20kHz
0.1
20Hz 0.01 1E-3 0.01 0.1 Output Power (W)
1kHz 1 0.01 1E-3
20Hz 0.01 0.1 Output Power (W)
1kHz 1
Fig. 29 : THD + N vs Output Power
10 RL = 8, Vcc = 3.3V Gv = 2 Cb = Cin = 1F BW < 125kHz Tamb = 25C
Fig. 30 : THD + N vs Output Power
10 RL = 8, Vcc = 3.3V Gv = 10 Cb = Cin = 1F BW < 125kHz Tamb = 25C 20Hz 0.1 20kHz 1kHz
THD + N (%)
1
0.1
20Hz
20kHz
1kHz 0.01 1E-3 0.01 0.1 Output Power (W) 1 0.01 1E-3
THD + N (%)
1
0.01 0.1 Output Power (W)
1
Fig. 31 : THD + N vs Output Power
10 RL = 8, Vcc = 2.6V Gv = 2 Cb = Cin = 1F BW < 125kHz Tamb = 25C
Fig. 32 : THD + N vs Output Power
10 RL = 8, Vcc = 2.6V Gv = 10 Cb = Cin = 1F BW < 125kHz Tamb = 25C 20Hz
THD + N (%)
1
0.1
20Hz
20kHz
THD + N (%)
1
0.1 20kHz 1kHz
1kHz 0.01 1E-3 0.01 0.1 Output Power (W) 0.01 1E-3
0.01 0.1 Output Power (W)
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TS4972
Fig. 33 : THD + N vs Output Power
10 RL = 8 Vcc = 5V Gv = 2 Cb = 0.1F, Cin = 1F BW < 125kHz Tamb = 25C
Fig. 34 : THD + N vs Output Power
10 RL = 8, Vcc = 5V, Gv = 10 Cb = 0.1F, Cin = 1F BW < 125kHz, Tamb = 25C
THD + N (%)
THD + N (%)
1
1 20Hz
20Hz
0.1
0.1 20kHz 20kHz 1kHz 0.01 0.1 Output Power (W) 1 0.01 1E-3 0.01 0.1 Output Power (W) 1 1kHz
0.01 1E-3
Fig. 35 : THD + N vs Output Power
10 RL = 8, Vcc = 3.3V Gv = 2 Cb = 0.1F, Cin = 1F BW < 125kHz Tamb = 25C
Fig. 36 : THD + N vs Output Power
10 RL = 8, Vcc = 3.3V, Gv = 10 Cb = 0.1F, Cin = 1F BW < 125kHz, Tamb = 25C
THD + N (%)
THD + N (%)
1
1 20Hz 20kHz 0.1
0.1
20Hz
20kHz
1kHz 1kHz 0.01 1E-3 0.01 0.1 Output Power (W) 1 0.01 1E-3 0.01 0.1 Output Power (W) 1
Fig. 37 : THD + N vs Output Power
10 RL = 8, Vcc = 2.6V Gv = 2 Cb = 0.1F, Cin = 1F BW < 125kHz Tamb = 25C
Fig. 38 : THD + N vs Output Power
10 RL = 8, Vcc = 2.6V, Gv = 10 Cb = 0.1F, Cin = 1F BW < 125kHz, Tamb = 25C
THD + N (%)
THD + N (%)
1
1 20kHz 0.1 1kHz 20Hz
0.1
20Hz
20kHz
1kHz 0.01 1E-3 0.01 0.1 Output Power (W) 0.01 1E-3 0.01 Output Power (W) 0.1
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TS4972
Fig. 39 : THD + N vs Output Power
10 RL = 16, Vcc = 5V Gv = 2 Cb = Cin = 1F BW < 125kHz Tamb = 25C
Fig. 40 : THD + N vs Output Power
10 RL = 16, Vcc = 5V Gv = 10 Cb = Cin = 1F BW < 125kHz Tamb = 25C
1
THD + N (%)
THD + N (%)
1
20kHz 0.1 20Hz
0.1
20Hz
20kHz
0.01 1E-3
1kHz 0.01 0.1 Output Power (W) 1
1kHz 0.01 1E-3 0.01 0.1 Output Power (W) 1
Fig. 41 : THD + N vs Output Power
10 RL = 16, Vcc = 3.3V Gv = 2 Cb = Cin = 1F BW < 125kHz Tamb = 25C
Fig. 42 : THD + N vs Output Power
10 RL = 16 Vcc = 3.3V Gv = 10 Cb = Cin = 1F BW < 125kHz Tamb = 25C 20Hz 0.1 20kHz
1
THD + N (%)
0.1 20Hz 20kHz
THD + N (%)
1
0.01 1E-3
1kHz 0.01 0.01 Output Power (W) 0.1 1E-3
1kHz 0.01 Output Power (W) 0.1
Fig. 43 : THD + N vs Output Power
10 RL = 16 Vcc = 2.6V Gv = 2 Cb = Cin = 1F BW < 125kHz Tamb = 25C
Fig. 44 : THD + N vs Output Power
10 RL = 16 Vcc = 2.6V Gv = 10 Cb = Cin = 1F BW < 125kHz Tamb = 25C 20Hz 0.1 20kHz
1
THD + N (%)
0.1
20Hz
20kHz
0.01 1E-3
1kHz 0.01 Output Power (W) 0.1 0.01 1E-3
THD + N (%)
1
1kHz 0.01 Output Power (W) 0.1
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TS4972
Fig. 45 : THD + N vs Frequency Fig. 46 : THD + N vs Frequency
1
0.1 Pout = 650mW
THD + N (%)
THD + N (%)
RL = 4, Vcc = 5V Gv = 2 Cb = 1F BW < 125kHz Tamb = 25C
1 Pout = 1.3W Pout = 1.3W
0.1 RL = 4, Vcc = 5V Gv = 10 Cb = 1F BW < 125kHz Tamb = 25C 0.01 20 100 1000 Frequency (Hz)
Pout = 650mW
0.01 20
100
1000 Frequency (Hz)
10000
10000
Fig. 47 : THD + N vs Frequency
Fig. 48 : THD + N vs Frequency
1
THD + N (%)
Pout = 560mW 0.1
THD + N (%)
RL = 4, Vcc = 3.3V Gv = 2 Cb = 1F BW < 125kHz Tamb = 25C
1
Pout = 560mW
RL = 4, Vcc = 3.3V Gv = 10 Cb = 1F BW < 125kHz Tamb = 25C
0.1
Pout = 280mW
Pout = 280mW 0.01 20 100 1000 Frequency (Hz) 10000
0.01 20
100
1000 Frequency (Hz)
10000
Fig. 49 : THD + N vs Frequency
Fig. 50 : THD + N vs Frequency
1
THD + N (%)
0.1
Pout = 240 & 120mW
THD + N (%)
RL = 4, Vcc = 2.6V Gv = 2 Cb = 1F BW < 125kHz Tamb = 25C
1
RL = 4, Vcc = 2.6V Gv = 10 Cb = 1F BW < 125kHz Tamb = 25C
0.1
Pout = 240 & 120mW
0.01 20
100
1000 Frequency (Hz)
10000
0.01 20
100
1000 Frequency (Hz)
10000
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TS4972
Fig. 51 : THD + N vs Frequency
1 RL = 8 Vcc = 5V Gv = 2 Pout = 920mW BW < 125kHz Tamb = 25C
Fig. 52 : THD + N vs Frequency
1 RL = 8 Vcc = 5V Gv = 2 Pout = 460mW BW < 125kHz Tamb = 25C
Cb = 0.1F THD + N (%)
Cb = 0.1F THD + N (%)
0.1
0.1
Cb = 1F 0.01 20 100 1000 Frequency (Hz) 10000 0.01 20
Cb = 1F 100 1000 Frequency (Hz) 10000
Fig. 53 : THD + N vs Frequency
Fig. 54 : THD + N vs Frequency
1
Cb = 0.1F
THD + N (%)
0.1
THD + N (%)
RL = 8, Vcc = 5V Gv = 10 Pout = 920mW BW < 125kHz Tamb = 25C
1
Cb = 0.1F
RL = 8, Vcc = 5V Gv = 10 Pout = 460mW BW < 125kHz Tamb = 25C
0.1
Cb = 1F 0.01 20 100 1000 Frequency (Hz) 10000 0.01 20
Cb = 1F 100 1000 Frequency (Hz) 10000
Fig. 55 : THD + N vs Frequency
1 RL = 8, Vcc = 3.3V Gv = 2 Pout = 420mW BW < 125kHz Tamb = 25C
Fig. 56 : THD + N vs Frequency
1 RL = 8, Vcc = 3.3V Gv = 2 Pout = 210mW BW < 125kHz Tamb = 25C
Cb = 0.1F THD + N (%)
Cb = 0.1F THD + N (%)
0.1
0.1
Cb = 1F 0.01 20 100 1000 Frequency (Hz) 10000 0.01 20
Cb = 1F 100 1000 Frequency (Hz) 10000
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TS4972
Fig. 57 : THD + N vs Frequency Fig. 58 : THD + N vs Frequency
1
Cb = 0.1F
THD + N (%)
0.1
THD + N (%)
RL = 8, Vcc = 3.3V Gv = 10 Pout = 420mW BW < 125kHz Tamb = 25C
1
Cb = 0.1F
RL = 8, Vcc = 3.3V Gv = 10 Pout = 210mW BW < 125kHz Tamb = 25C
0.1
Cb = 1F 0.01 20 0.01 20
Cb = 1F
100
1000 Frequency (Hz)
10000
100
1000 Frequency (Hz)
10000
Fig. 59 : THD + N vs Frequency
1 RL = 8, Vcc = 2.6V Gv = 2 Pout = 220mW BW < 125kHz Tamb = 25C
Fig. 60 : THD + N vs Frequency
1 RL = 8, Vcc = 2.6V Gv = 10 Pout = 110mW BW < 125kHz Tamb = 25C
THD + N (%)
0.1
THD + N (%)
Cb = 0.1F
Cb = 0.1F 0.1
Cb = 1F 0.01 20 100 1000 Frequency (Hz) 10000 0.01 20
Cb = 1F 100 1000 Frequency (Hz) 10000
Fig. 61 : THD + N vs Frequency
Fig. 62 : THD + N vs Frequency
1
Cb = 0.1F
THD + N (%)
0.1
THD + N (%)
RL = 8, Vcc = 2.6V Gv = 10 Pout = 220mW BW < 125kHz Tamb = 25C
1
Cb = 0.1F
RL = 8, Vcc = 2.6V Gv = 10 Pout = 110mW BW < 125kHz Tamb = 25C
0.1
Cb = 1F 0.01 20 0.01 20
Cb = 1F 1000 Frequency (Hz) 10000 100 1000 Frequency (Hz) 10000
100
15/28
TS4972
Fig. 63 : THD + N vs Frequency
0.1
RL = 16, Vcc = 5V Gv = 10, Cb = 1F BW < 125kHz Tamb = 25C
Fig. 64 : THD + N vs Frequency
Pout = 315mW
THD + N (%)
THD + N (%)
0.1
0.01
Pout = 315mW
Pout = 630mW
RL = 16, Vcc = 5V Gv = 2, Cb = 1F BW < 125kHz Tamb = 25C 1000 Frequency (Hz) 10000
0.01 20
Pout = 630mW 100 1000 Frequency (Hz) 10000
1E-3 20
100
Fig. 65 : THD + N vs Frequency
0.1
Fig. 66 : THD + N vs Frequency
1 RL = 16, Vcc = 3.3V Gv = 10, Cb = 1F BW < 125kHz Tamb = 25C
THD + N (%)
THD + N (%)
Pout = 140mW 0.01
0.1 Pout = 140mW
Pout = 280mW
Pout = 280mW
RL = 16, Vcc = 3.3V Gv = 2, Cb = 1F BW < 125kHz Tamb = 25C 1000 Frequency (Hz) 10000 0.01 20 100 1000 Frequency (Hz) 10000
1E-3 20
100
Fig. 67 : THD + N vs Frequency
0.1
Fig. 68 : THD + N vs Frequency
1 RL = 16, Vcc = 2.6V Gv = 10, Cb = 1F BW < 125kHz Tamb = 25C
THD + N (%)
0.01 Pout = 160mW RL = 16, Vcc = 2.6V Gv = 2, Cb = 1F BW < 125kHz Tamb = 25C 1E-3 20 100 1000 Frequency (Hz) 10000
THD + N (%)
Pout = 80mW
Pout = 160mW
0.1
Pout = 80mW 0.01 20 100 1000 Frequency (Hz) 10000
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TS4972
Fig. 69 : Signal to Noise Ratio vs Power Supply with Unweighted Filter (20Hz to 20kHz)
100
Fig. 70 : Signal to Noise Ratio vs Power Supply with Unweighted Filter (20Hz to 20kHz)
90
90
80
RL=16
SNR (dB)
RL=8
RL=4
SNR (dB)
80
RL=8 70 RL=16 RL=4
70 Gv = 2 Cb = Cin = 1F THD+N < 0.4% Tamb = 25C 3.0 3.5
Vcc (V)
60
60
50 2.5
Gv = 10 Cb = Cin = 1F THD+N < 0.7% Tamb = 25C 3.0 3.5
Vcc (V)
4.0
4.5
5.0
50 2.5
4.0
4.5
5.0
Fig. 71 : Signal to Noise Ratio vs Power Supply with Weighted Filter Type A
110
Fig. 72 : Signal to Noise Ratio vs Power Supply with Weighted Filter Type A
100
100
90
RL=16
SNR (dB)
RL=8
RL=4
SNR (dB)
90
RL=8 80 RL=16 RL=4
80 Gv = 2 Cb = Cin = 1F THD+N < 0.4% Tamb = 25C 3.0 3.5
Vcc (V)
70
70
60 2.5
Gv = 10 Cb = Cin = 1F THD+N < 0.7% Tamb = 25C 3.0 3.5
Vcc (V)
4.0
4.5
5.0
60 2.5
4.0
4.5
5.0
Fig. 73 : Frequency Response Gain vs Cin, & Cfeed
10 5 0
Gain (dB)
Fig. 74 : Current Consumption vs Power Supply Voltage
7 6 Vstandby = 0V Tamb = 25C
Cfeed = 330pF
Icc (mA)
5 4 3 2
-5 -10 -15 -20 -25 10 Cin = 470nF Cin = 22nF Cin = 82nF
Cfeed = 680pF Cfeed = 2.2nF
Rin = Rfeed = 22k Tamb = 25C 10000
1 0
100 1000 Frequency (Hz)
0
1
2
Vcc (V)
3
4
5
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TS4972
Fig. 75 : Current Consumption vs Standby Voltage @ Vcc = 5V
7 6 5
Icc (mA)
Fig. 76 : Current Consumption vs Standby Voltage @ Vcc = 3.3V
6
Vcc = 5V Tamb = 25C
5 4
Icc (mA)
Vcc = 3.3V Tamb = 25C
4 3 2 1 0 0.0
3 2 1 0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.5
1.0
1.5
2.0
2.5
3.0
Vstandby (V)
Vstandby (V)
Fig. 77 : Current Consumption vs Standby Voltage @ Vcc = 2.6V
6
Fig. 78 : Clipping Voltage vs Power Supply Voltage and Load Resistor
0.6 Vout1 & Vout2 Clipping Voltage High side (V)
5 4
Icc (mA)
Vcc = 2.6V Tamb = 25C
Tamb = 25C 0.5 0.4
RL = 4
RL = 8 0.3 0.2 0.1 RL = 16 0.0 2.5
3 2 1 0 0.0
0.5
1.0 1.5 Vstandby (V)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Power supply Voltage (V)
Fig. 79 : Clipping Voltage vs Power Supply Voltage and Load Resistor
0.7 0.6 0.5 0.4 RL = 8 0.3 0.2 0.1 RL = 16 0.0 2.5 3.0 3.5 4.0 4.5 5.0 Tamb = 25C RL = 4
Vout1 & Vout2 Clipping Voltage Low side (V)
Power supply Voltage (V)
18/28
TS4972
APPLICATION INFORMATION Fig. 80 : Demoboard Schematic
S1
VCC
VCC C1
Vcc S2
GND
R2 GND R1
C2
VCC
P1 Neg. Input 6 R3 C3
+
C6 100
C7 100n U1 S6
R4 P2 Pos. Input C4 R5
C5 1 Vin-
VC C Vout 1 8
OUT1 C9
+
S3 GND S4 GND
7
Vin+
+
470
S5 Positive Input mode
R6 S7 C10 Vout 2 4
+
VCC 3 R7 100k S8 R8 1k Standby C11 +
+
AV = -1 Bypass +
OUT2
470
5
Standby
Bias
G C12 1u 2 ND C8 100n
TS4972
Fig. 81 : Flip-Chip 300m Demoboard Components Side
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TS4972
Fig. 82 : Flip-Chip 300m Demoboard Top Solder Layer The output power is:
Pout = ( 2 Vout RMS ) 2 (W ) RL
For the same power supply voltage, the output power in BTL configuration is four times higher than the output power in single ended configuration.
s Gain In Typical Application Schematic
(cf. page 1) In flat region (no effect of Cin), the output voltage of the first stage is: R fe ed Vout1 = - Vin ------------------- (V) Rin For the second stage : Vout2 = -Vout1 (V) Fig. 83 : Flip-Chip 300m Demoboard Bottom
Solder Layer
The differential output voltage is: Rfee d Vout2 - Vo ut1 = 2Vin ------------------- (V) Rin The differential gain named gain (Gv) for more convenient usage is: Vout2 - Vou t1 Rfee d Gv = -------------------------------------- = 2 ------------------Vin Rin Remark : Vout2 is in phase with Vin and Vout1 is 180 phased with Vin. It means that the positive terminal of the loudspeaker should be connected to Vout2 and the negative to Vout1.
s Low and high frequency response
In low frequency region, the effect of Cin starts. Cin with Rin forms a high pass filter with a -3dB cut off frequency. 1 FCL = ------------------------------- ( Hz ) 2 R in Cin In high frequency region, you can limit the bandwidth by adding a capacitor (Cfeed) in parallel on Rfeed. Its form a low pass filter with a -3dB cut off frequency. 1 FCH = ---------------------------------------------- ( Hz ) 2 Rfe ed Cfeed
s BTL Configuration Principle
The TS4972 is a monolithic power amplifier with a BTL output type. BTL (Bridge Tied Load) means that each end of the load is connected to two single ended output amplifiers. Thus, we have : Single ended output 1 = Vout1 = Vout (V) Single ended output 2 = Vout2 = -Vout (V) And Vout1 - Vout2 = 2Vout (V)
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TS4972 s Power dissipation and efficiency
Hypothesis : * Voltage and current in the load are sinusoidal (Vout and Iout) * Supply voltage is a pure DC source (Vcc) Regarding the load we have: VOUT = V PEAK sin t (V) and VOUT IOUT = ---------------- (A) RL and VPEAK POUT = ---------------------- (W) 2 RL Then, the average current delivered by the supply voltage is: ICC
AVG 2
The maximum theoretical value is reached when Vpeak = Vcc, so ---- = 78.5% 4
s Decoupling of the circuit
Two capacitors are needed to bypass properly the TS4972, a power supply bypass capacitor Cs and a bias voltage bypass capacitor Cb. Cs has especially an influence on the THD+N in high frequency (above 7kHz) and indirectly on the power supply disturbances. With 100F, you can expect similar THD+N performances like shown in the datasheet. If Cs is lower than 100F, in high frequency increases, THD+N and disturbances on the power supply rail are less filtered. To the contrary, if Cs is higher than 100F, those disturbances on the power supply rail are more filtered. Cb has an influence on THD+N in lower frequency, but its function is critical on the final result of PSRR with input grounded in lower frequency. If Cb is lower than 1F, THD+N increase in lower frequency (see THD+N vs frequency curves) and the PSRR worsens up If Cb is higher than 1F, the benefit on THD+N in lower frequency is small but the benefit on PSRR is substantial (see PSRR vs. Cb curve : fig.12). Note that Cin has a non-negligible effect on PSRR in lower frequency. Lower is its value, higher is the PSRR (see fig. 13).
VPEAK = 2 ------------------- (A) RL
The power delivered by the supply voltage is Psupply = Vcc IccAVG (W) Then, the power dissipated by the amplifier is Pdiss = Psupply - Pout (W) 2 2 Vcc Pdi ss = ---------------------- POUT - POUT (W) RL and the maximum value is obtained when: Pdiss --------------------- = 0 POUT and its value is:
s Pop and Click performance
Pop and Click performance is intimately linked with the size of the input capacitor Cin and the bias voltage bypass capacitor Cb. Size of Cin is due to the lower cut-off frequency and PSRR value requested. Size of Cb is due to THD+N and PSRR requested always in lower frequency. Moreover, Cb determines the speed that the amplifier turns ON. The slower the speed is, the softer the turn ON noise is.
Pdiss max =
2 Vcc
2
2RL
(W)
Remark : This maximum value is only depending on power supply voltage and load values. The efficiency is the ratio between the output power and the power supply VPEAK POUT = ----------------------- = ---------------------Psup ply 4VCC
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TS4972
The charge time of Cb is directly proportional to the internal generator resistance 50k. Then, the charge time constant for Cb is b = 50kxCb (s) As Cb is directly connected to the non-inverting input (pin 2 & 3) and if we want to minimize, in amplitude and duration, the output spike on Vout1 (pin 5), Cin must be charged faster than Cb. The charge time constant of Cin is in = (Rin+Rfeed)xCin (s) Thus we have the relation in << b (s) The respect of this relation permits to minimize the pop and click noise. Remark : Minimize Cin and Cb has a benefit on pop and click phenomena but also on cost and size of the application. Example : your target for the -3dB cut off frequency is 100 Hz. With Rin=Rfeed=22 k, Cin=72nF (in fact 82nF or 100nF). With Cb=1F, if you choose the one of the latest two values of Cin, the pop and click phenomena at power supply ON or standby function ON/OFF will be very small 50 kx1F >> 44kx100nF (50ms >> 4.4ms). Increasing Cin value increases the pop and click phenomena to an unpleasant sound at power supply ON and standby function ON/OFF. Why Cs is not important in pop and click consideration ? Hypothesis : * Cs = 100F * Supply voltage = 5V * Supply voltage internal resistor = 0.1 * Supply current of the amplifier Icc = 6mA At power ON of the supply, the supply capacitor is charged through the internal power supply resistor. So, to reach 5V you need about five to ten times the charging time constant of Cs (s = 0.1xCs (s)). Then, this time equal 50s to 100s << b in the majority of application. At power OFF of the supply, Cs is discharged by a constant current Icc. The discharge time from 5V to 0V of Cs is:
22/28
5Cs tDischCs = ------------- = 83 ms Icc Now, we must consider the discharge time of Cb. At power OFF or standby ON, Cb is discharged by a 100k resistor. So the discharge time is about bDisch 3xCbx100k (s). In the majority of application, Cb=1F, then bDisch300ms >> tdischCs.
s Power amplifier design examples
Given : * * * * * * * Load impedance : 8 Output power @ 1% THD+N : 0.5W Input impedance : 10k min. Input voltage peak to peak : 1Vpp Bandwidth frequency : 20Hz to 20kHz (0, -3dB) Ambient temperature max = 50C SO8 package
First of all, we must calculate the minimum power supply voltage to obtain 0.5W into 8. With curves in fig. 15, we can read 3.5V. Thus, the power supply voltage value min. will be 3.5V. Following equation the maximum power dissipation
Pdiss max =
2 Vcc 2 2RL
(W)
with 3.5V we have Pdissmax=0.31W. Refer to power derating curves (fig. 20), with 0.31W the maximum ambient temperature will be 100C. This last value could be higher if you follow the example layout shown on the demoboard (better dissipation). The gain of the amplifier in flat region will be: VOUTPP 2 2 RL P OUT G V = -------------------- = ----------------------------------- = 5.65 VINPP VINPP We have Rin > 10k. Let's take Rin = 10k, then Rfeed = 28.25k. We could use for Rfeed = 30k in normalized value and the gain will be Gv = 6.
TS4972
In lower frequency we want 20 Hz (-3dB cut off frequency). Then: 1 CIN = ----------------------------- = 795nF 2 RinFCL So, we could use for Cin a 1F capacitor value which gives 16Hz. In Higher frequency we want 20kHz (-3dB cut off frequency). The Gain Bandwidth Product of the TS4972 is 2MHz typical and doesn't change when the amplifier delivers power into the load. The first amplifier has a gain of: Rfee d ----------------- = 3 R in and the theoretical value of the -3dB cut-off higher frequency is 2MHz/3 = 660kHz. We can keep this value or limit the bandwidth by adding a capacitor Cfeed, in parallel on Rfeed. Then: 1 C FE E D = -------------------------------------- = 265pF 2 R F E E DFC H So, we could use for Cfeed a 220pF capacitor value that gives 24kHz. Now, we can calculate the value of Cb with the formula b = 50kxCb >> in = (Rin+Rfeed)xCin which permits to reduce the pop and click effects. Then Cb >> 0.8F. We can choose for Cb a normalized value of 2.2F that gives good results in THD+N and PSRR. In the following tables, you could find three another examples with values required for the demoboard. Application n1 : 20Hz to 20kHz bandwidth and 6dB gain BTL power amplifier. Components :
Designator R1 R4 R6 R7 Part Type 22k / 0.125W S8 22k / 0.125W Short Cicuit 100k / 0.125W P1 R8 C5 C6 C7 C9 C10 C12 S1, S2, S6, S7 S8 P1
Designator
Part Type Short Circuit 470nF 100F 100nF Short Circuit Short Circuit 1F 2mm insulated Plug 10.16mm pitch 3 pts connector 2.54mm pitch SMB Plug
Application n2 : 20Hz to 20kHz bandwidth and 20dB gain BTL power amplifier. Components :
Designator R1 R4 R6 R7 R8 C5 C6 C7 C9 C10 C12 S1, S2, S6, S7 Part Type 110k / 0.125W 22k / 0.125W Short Cicuit 100k / 0.125W Short Cicuit 470nF 100F 100nF Short Circuit Short Circuit 1F 2mm insulated Plug 10.16mm pitch 3 pts connector 2.54mm pitch SMB Plug
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TS4972
Application n3 : 50Hz to 10kHz bandwidth and 10dB gain BTL power amplifier. Components :
40
Fig. 84 : Minimum Differential Gain vs Power Supply
Voltage
Designator R1 R2 R4 R6 R7 R8 C2 C5 C6 C7 C9 C10 C12 S1, S2, S6, S7 S8 P1
Part Type
35 Differential Gain min. (dB)
33k / 0.125W Short Circuit 22k / 0.125W Short Cicuit 100k / 0.125W Short Cicuit 470pF 150nF 100F 100nF Short Circuit Short Circuit
30 25 20 15 10 2.5
3.0
3.5 4.0 4.5 Power Supply Voltage (V)
5.0
5.5
For Vcc=5V, a 20Hz to 20kHz bandwidth and 20dB gain BTL power amplifier you could follow the bill of material below. Components :
Designator Part Type 110k / 0.125W 22k / 0.125W 22k / 0.125W 110k / 0.125W 100k / 0.125W Short circuit 470nF 470nF 100F 100nF Short Circuit Short Circuit 1F
1F 2mm insulated Plug 10.16mm pitch 3 pts connector 2.54mm pitch SMB Plug R7 R8 C4 C5 C6 R1 R4 R5 R6
Application n4 : Differential inputs BTL power amplifier. In this configuration, we need to place these components : R1, R4, R5, R6, R7, C4, C5, C12. We have also : R4 = R5, R1 = R6, C4 = C5. The differential gain of the amplifier is: R1 GVDIFF = 2 ------R4 Note : Due to the VICM range (see Operating Condition), GVDIFF must have a minimum value shown in figure 84.
C7 C9 C10 C12
S1, S2, S6, S7
2mm insulated Plug 10.16mm pitch
3 pts connector 2.54mm pitch SMB Plug
S8 P1, P2
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TS4972 s Note on how to use the PSRR curves
(page 7) We have finished a design and we have chosen the components values : * Rin=Rfeed=22k * Cin=100nF * Cb=1F Now, on fig. 13, we can see the PSRR (input grounded) vs frequency curves. At 217Hz we have a PSRR value of -36dB. In reality we want a value about -70dB. So, we need a gain of 34dB ! Now, on fig. 12 we can see the effect of Cb on the PSRR (input grounded) vs. frequency. With Cb=100F, we can reach the -70dB value. The process to obtain the final curve (Cb=100F, Cin=100nF, Rin=Rfeed=22k) is a simple transfer point by point on each frequency of the curve on fig. 13 to the curve on fig. 12. The measurement result is shown on the next figure. Fig. 85 : PSRR changes with Cb Fig. 86 : PSRR measurement schematic How we measure the PSRR ?
Rfeed Vripple 6 VCC 1 VinVout 1 Rin Cin 7 Vin+ + RL 8
Vs-
Vcc
AV = -1 3 Rg 100 Ohms Bypass + Vout 2 4
Vs+
5
Standby
Bias GND
TS4972 Cb 2
s Principle of operation
* We fixed the DC voltage supply (Vcc) * We fixed the AC sinusoidal ripple voltage (Vripple) * No bypass capacitor Cs is used The PSRR value for each frequency is:
-30 Cin=100nF Cb=1F
-40
PSRR (dB)
Vcc = 5, 3.3 & 2.6V Rfeed = 22k, Rin = 22k Rg = 100, RL = 8 Tamb = 25C
PSRR ( d B ) = 20 x Log 10
R ms ( Vrippl e ) -------------------------------------------Rms ( Vs + - Vs - )
-50 Cin=100nF Cb=100F
Remark : The measure of the Rms voltage is not a Rms selective measure but a full range (2 Hz to 125 kHz) Rms measure. It means that we measure the effective Rms signal + the noise.
-60
-70 10 100 1000
Frequency (Hz)
10000
100000
s Note on PSRR measurement
What is the PSRR ? The PSRR is the Power Supply Rejection Ratio. It's a kind of SVR in a determined frequency range. The PSRR of a device, is the ratio between a power supply disturbance and the result on the output. We can say that the PSRR is the ability of a device to minimize the impact of power supply disturbances to the output.
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TS4972
Fig. 87 :TS4972 Footprint Recommendation (Non Solder Mask Defined)
500m =250m Track 500m 75m min. 100m max.
Solder mask opening
500m
500m
=400m
150m min.
Pad in Cu 35m with Flash NiAu (6m, 0.15m)
TOP VIEW OF THE DAISY CHAIN MECHANICAL DATA ( all drawings dimensions are in millimeters )
7
Vin+
6
Vcc
5
Stdby
8
Vout1
Vout2
4 1.6 mm
Vin
Gnd
Bypass
1
2 2.26 mm
3
REMARKS Daisy chain sample is featuring pins connection two by two. The schematic above is illustrating the way connecting pins each other. This sample is used for testing continuity on board. PCB needs to be designed on the opposite way, where pin connections are not done on daisy chain samples. By that way, just connecting an Ohmeter between pin 8 and pin 1, the soldering process continuity can be tested. ORDER CODE
Part Number TSDC03IJT 26/28 Temperature Range -40, +85C Package Marking J * DC3
TS4972
TAPE & REEL SPECIFICATION ( top view )
User direction of feed
4972 A72
4972 A72
27/28
TS4972
PIN OUT (Top View)
7
Vin
+
MARKING (Top View)
6
Vcc
5
Stdby
8
Vout1
Vout2
4
Vin
Gnd
Bypass
1
2
3
s Balls are underneath
PACKAGE MECHANICAL DATA FLIP CHIP - 8 BUMPS
0.5 0.5
1.6
s s s s s
Die size : (2.26mm 10%) x (1.6mm 10%) Die height (including bumps) : 650m 50 Bumps diameter : 315m 15m Silicon thickness : 400m 25m Pitch: 500m 10m
0.5 0.5
2.26
400m 650m 250m
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom http://www.st.com
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